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-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:21:41 12/07/2009 
-- Design Name: 
-- Module Name:    datapath - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.MIPS_IR.ALL;
use WORK.MIPS_RF.ALL;
use WORK.MIPS_REGISTER.ALL;
use WORK.MIPS_ALU.ALL;
use WORK.MIPS_ALU_CTRL.ALL;
use WORK.MIPS_MUX.ALL;


---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity datapath is
    Port ( IR : in  STD_LOGIC_VECTOR (31 downto 0);
           MDR : in  STD_LOGIC_VECTOR (15 downto 0);
           clock : in  STD_LOGIC;
			  zero, carry : out STD_LOGIC;
           ALU_res : out  STD_LOGIC_VECTOR (15 downto 0));
end datapath;

architecture Behavioral of datapath is

signal Wr_data, Reg1, Reg2, alu_InA, alu_InB, alu_Out, result :  STD_LOGIC_VECTOR (15 downto 0);
signal OP, funct : STD_LOGIC_VECTOR (5 downto 0);
signal rs, rt, rd, shift : STD_LOGIC_VECTOR (4 downto 0);
signal ctrl : STD_LOGIC_VECTOR (2 downto 0);
signal RegWrite : STD_LOGIC;

begin
	dat_IR : InstructionRegister
		port map(IR, clock, OP, rs, rt, rd, shift, funct);
		
	dat_RF : RegisterFile
		port map(rs(1 downto 0), rt(1 downto 0), rd(1 downto 0), alu_Out, RegWrite, Reg1, Reg2);

	dat_ALU : ALU
		port map(ctrl, alu_InA, alu_InB, result, zero, carry);

	dat_Control : ALU_control
		port map(funct, ctrl);		
		
	ALU_res <= alu_Out;
		
	dat_RegA : Reg_16bit
		port map(clock, '1', Reg1, alu_InA);
	dat_RegB : Reg_16bit
		port map(clock, '1', Reg2, alu_InB);
	dat_ALUout : Reg_16bit
		port map(clock, '1', result, alu_Out);		
	
end Behavioral;

